Title:
SEMICONDUCTOR MEMORY EVALUATION DEVICE
Document Type and Number:
Japanese Patent JPH01140500
Kind Code:
A
Abstract:
PURPOSE:To obtain a high defect detecting efficiency according to a measurement for a short time by using a random pattern generator for generating a test pattern. CONSTITUTION:The random pattern generator 20 generates an address, data and a control signal by timing outputting from a timing generator 1 at random. A logic selector 21 receives the output of an algorithmic pattern generator 2 and the output of the random pattern generator 20, selects one of them and outputs as the test pattern or takes both the logics and outputs as the test pattern. In a pattern trace memory 22, the output of the logic selector 21, namely, the test patterns of the address, the data and the control signal are stored in respective steps and for every pin. Accordingly, even when the test patterns are generated at random, whether or no test pattern generates a defect is detected. Thereby, the high defect detecting efficiency is obtained with the measurement for a short time.
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Inventors:
SATO KATSUHIKO
Application Number:
JP29921087A
Publication Date:
June 01, 1989
Filing Date:
November 27, 1987
Export Citation:
Assignee:
TOSHIBA CORP
International Classes:
G01R31/3183; G11C29/10; G11C29/00; (IPC1-7): G11C29/00
Attorney, Agent or Firm:
Takehiko Suzue (2 outside)