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Title:
半導体メモリ及びその製造方法
Document Type and Number:
Japanese Patent JP3948629
Kind Code:
B2
Abstract:
A semiconductor memory which is improved in reliability by preventing the lowering of capacitance and defective insulation, especially, electrode delamination caused by the formation of the passivation film (insulating film) of a capacitor using a high- dielectric- constant or ferroelectric material by plasma processing at a relatively low temperature and a method for manufacturing the memory. The semiconductor memory has an integrated capacitor composed of a capacitor structure constituted of an upper electrode, a lower electrode, and a capacitor insulating film (of a high- dielectric- constant or ferroelectric thin film) which is held between electrodes and serves as a capacitor insulating film and a protective insulating film which covers the capacitor structure and is formed by plasma treatment. An oxygen introducing layer is further formed on the surface of the thin film constituting the capacitor insulating film. In the manufacturing process of the memory, for example, the oxygen introducing layer is formed on the surface of the high- dielectric- constant or ferroelectric material by introducing oxygen to the boundary between the electrode and the material by conducting heat treatment in an oxygen atmosphere before the protective insulating film (SiO2 passivation film) is formed by plasma treatment after the formation of the electrode. Therefore, lowering of capacitance, defective insulation, and especially, electrode delamination, which are caused by the formation of the passivation film (insulating film), can be prevented. In addition, the occurrence of defective insulation can be reduced by suppressing the lowering of the capacitance when an alternating electric field is impressed. When a ferroelectric material is used as the dielectric film, moreover, such an effect as an increase in residual polarization, a decrease in coercive voltage, etc., can be obtained.

Inventors:
Hiroshi Miki
Keiko Kushida
Yoshihisa Fujisaki
Application Number:
JP50504798A
Publication Date:
July 25, 2007
Filing Date:
July 04, 1997
Export Citation:
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Assignee:
Renesas Technology Corp.
International Classes:
H01L21/8242; H01L21/02; H01L27/108; H01L21/314; H01L21/316
Domestic Patent References:
JP7093969A
JP8078636A
JP7263570A
JP8055967A
Attorney, Agent or Firm:
Polaire Patent Business Corporation
Katsuo Ogawa