To allow even anomalies in a semiconductor memory storage device due to failures in semiconductor memory chips to be solved without replacement of a memory unit.
The semiconductor memory storage device writes an input information signal to the memory unit 11 after compression in an encoder 10. The signal read out from the memory unit 11 is output after decoding in a decoder 12. The memory unit 11 comprises two types of boards comprising sub boards 20-1 to 20-256 mounted with the NAND semiconductor memory chips 21-1 to 21-256, and a main board 30 having sub board slots 31-1 to 31-256 where the respective sub boards 20-1 to 20-256 can be removably mounted. When the NAND semiconductor memory chip mounted on any sub board fails, a CPU 34 mounted on the main board 30 identifies the sub board mounted with the failed NAND semiconductor memory chip.
JP2004343682A | 2004-12-02 | |||
JP2002033946A | 2002-01-31 | |||
JPH10336562A | 1998-12-18 | |||
JP2005301831A | 2005-10-27 |
Satoshi Kono
Makoto Nakamura
Kurata Masatoshi
Takashi Mine
Yoshihiro Fukuhara
Sadao Muramatsu
Ryo Hashimoto
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