Title:
SEMICONDUCTOR MEMORY STORAGE
Document Type and Number:
Japanese Patent JP3202580
Kind Code:
B2
Abstract:
PURPOSE: To provide a layout to minimize the used area in a semiconductor memory storage by arranging an MDQ switch and the additional circuits such as a sensing amplifier driving circuit, etc.
CONSTITUTION: This semiconductor memory storage is provided with a bit line couple BL and /BL, connected respectively to a corresponding row memory cells in a memory cell array, sensing amplifiers 22 and 24 with which data is sensed by being coupled to the bit line couple BL and /BL, and a column switch 25 which outputs complementary data to a data line. The sensing amplifiers 22 and 24 and the column switch 25 are arranged on a semiconductor chip in such a manner that they have the pitch twice the pitch of the bit line couple BL and /BL or less in circuit arrangement arranged on both sides of the memory array.
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Inventors:
Daisuke Kato
Yoji Watanabe
Yoji Watanabe
Application Number:
JP5324796A
Publication Date:
August 27, 2001
Filing Date:
March 11, 1996
Export Citation:
Assignee:
Toshiba Corporation
International Classes:
G11C11/401; G11C5/02; G11C11/409; G11C11/4091; G11C11/4096; H01L21/8242; H01L27/108; (IPC1-7): H01L27/108; G11C11/401; H01L21/8242
Domestic Patent References:
| JP335490A | ||||
| JP218778A | ||||
| JP2166690A | ||||
| JP4205876A |
Attorney, Agent or Firm:
Takehiko Suzue