Title:
SEMICONDUCTOR MEMORY TESTER
Document Type and Number:
Japanese Patent JPH06313794
Kind Code:
A
Abstract:
PURPOSE: To obtain a semiconductor memory tester which makes it possible to overwrite pass information in an address of a fail analysis memory.
CONSTITUTION: In a semiconductor memory tester equipped with a timing generator 10, a test pattern generator 20, a wave shaping unit 30, a logical comparator 40 and a fail analysis memory 50, a multiplexer 60 connected between logical output terminals of the logical comparator 40 outputting a pass signal '0' and a fail signal '1' and data terminals of the fail analysis memory 50 is provided. Through this multiplexer 60, the pass signal is supplied to an address of the fail analysis memory 50 only at a cycle being specifiable arbitrarily.
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Inventors:
OKAZAKI TADASHI
Application Number:
JP10411693A
Publication Date:
November 08, 1994
Filing Date:
April 30, 1993
Export Citation:
Assignee:
ADVANTEST CORP
International Classes:
G11C29/00; G11C29/56; G01R31/28; (IPC1-7): G01R31/318; G11C29/00
Attorney, Agent or Firm:
Kusano Taku (1 person outside)