To provide a semiconductor memory in which a memory cell can be initialized at high speed without increasing chip area.

This semiconductor memory has: a plurality of memory cells provided at the intersections of a plurality of word lines and a plurality of data lines; an initialization level means making the plurality of data lines an initialization level when an initialization signal is at an activation level; a delay circuit to which an initialization signal is inputted and which generates a plurality of delay initialization signals whose delay time are all different for the initialization signals; and a plurality of logic gates whose outputs are connected to the plurality of word lines respectively, whose input is one of the delay initialization signals, and in which a word line connected when a delay initialization signal is made an activation level is made an activation level.