To provide a semiconductor memory in which a high speed cycle time is attained while improving the operation convenience.
This device is provided with a first memory operation in which read or write of stored information is performed for a memory cell requiring periodic refresh-operation for holding stored information, and a time-multi-mode in which a second memory operation being a refresh-operation is performed before or after the first memory operation when the second memory operation being different from the first memory operation and specified by an address and refresh-operation conflict temporally. The shortest access time required for the first memory operation and the second memory operation or the refresh- operation performed before or after that is made shorter than a time obtained by adding a time required for the first memory operation and a time required for the second memory operation or the refresh-operation, on condition that stored information of the memory cell is not affected one another in the first memory operation and the second memory operation or the refresh-operation.
| JP4416372 | Semiconductor storage device |
| JP2000011641 | SEMICONDUCTOR MEMORY |
| JPH0229986 | SEMICONDUCTOR MEMORY AND ONE CHIP MICROCOMPUTER PROVIDING IT |
HORIGUCHI SHINJI
NAKAGOME YOSHINOBU
SAITO YOSHIKAZU
