To provide a semiconductor memory in which high speed read-out of data being equal to 'pipeline read-out' can be performed and chip area can be reduced.
This device is provided with a sense amplifier 4 sensing data from a memory cell array 1, column gates 3 connected in series by two stages or more, column gate driving circuits 5, 6 selecting and driving this gate 3, a data latch 7 latching sensed data, a multiplexer 9 selecting successively latched data and transmitting it to an output section (Data Out), and an address control circuit 8 selecting a column specified by an address selected next by reversing a driving signal driving at least one stage out of the gates 3 while this multiplexer 9 selects successively data, and sensing data in accordance with an address selected next by the sense amplifier 4.
TAKANO YOSHINORI
TANZAWA TORU
ATSUMI SHIGERU
