Title:
半導体メモリ
Document Type and Number:
Japanese Patent JP3741534
Kind Code:
B2
Abstract:
A semiconductor memory device includes a plurality of memory arrays which are provided on a semiconductor chip, the memory arrays including a predetermined memory array. A plurality of bias-voltage supply circuits respectively supply operating voltages to the memory arrays, the bias-voltage supply circuits including a predetermined supply circuit which supplies an operating voltage to the predetermined memory array. A control circuit controls the bias-voltage supply circuits respectively when a command is externally transmitted to the control circuit. The control circuit outputs a disable signal to the predetermined supply circuit in response to a partial-sleep-mode set command externally transmitted thereto, the disable signal causing the predetermined supply circuit to stop supplying the operating voltage to the predetermined memory array. The control circuit outputs an enable signal to the predetermined supply circuit in response to a cancel command externally transmitted thereto, the enable signal causing the predetermined supply circuit to start the supply of the operating voltage to the predetermined memory array.
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Inventors:
Hirohisa Abe
Application Number:
JP7538798A
Publication Date:
February 01, 2006
Filing Date:
March 24, 1998
Export Citation:
Assignee:
株式会社リコー
International Classes:
G11C11/413; G11C16/06; G11C5/14; G11C7/22; G11C11/407
Domestic Patent References:
| JP9204790A |
Attorney, Agent or Firm:
Aoyama Aoi
Osamu Kawamiya
Akihiro Shimada
Osamu Kawamiya
Akihiro Shimada
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