Title:
SEMICONDUCTOR MEMORY
Document Type and Number:
Japanese Patent JPH01117058
Kind Code:
A
Abstract:
PURPOSE:To reduce the size of wiring region and to minimize the area of a memory cell, by forming grooves within all element isolating region formed between memory cells or in a memory cell, and filling the grooves with a wiring metal so that they serve as word lines of the memory. CONSTITUTION:Following to formation of a groove isolating region and an element region, an aperture is formed in a part of an insulating film 9 where a buried word line is to be formed. Polycrystalline silicon 7 is etched by the ion etching process so as to form grooves and a silicon nitride film 10 is deposited to cover all the surface. Then, aluminum films 11a, 11b are formed by sputtering and the grooves are buried with resist 12. The resist 12 is then etched by the etch-back process until the aluminum film 11a is exposed. Further, the aluminum film 11a is removed by the plasma etching. The resist 12 in the grooves is etched off and gold layers 13 are formed within the grooves by the electroless plating. Finally, a silicon oxide film 14 is formed all over the surface.
Inventors:
SUGIYAMA MITSUHIRO
Application Number:
JP27515487A
Publication Date:
May 09, 1989
Filing Date:
October 29, 1987
Export Citation:
Assignee:
NEC CORP
International Classes:
G11C11/401; H01L21/3205; H01L21/331; H01L21/8222; H01L21/8229; H01L23/52; H01L27/06; H01L27/102; H01L27/11; H01L29/73; (IPC1-7): G11C11/34; H01L21/88; H01L27/06; H01L27/10; H01L29/72
Domestic Patent References:
| JPS62120048A | 1987-06-01 | |||
| JPS59155944A | 1984-09-05 |
Attorney, Agent or Firm:
Naoki Kyomoto (2 outside)
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