PURPOSE: To execute a read-out operation by the data rate of a higher speed than that of a conventional semiconductor memory by cascading and providing a switch circuit on one or plural cascade connection points of sense amplifiers which are subjected to cascade connection.

CONSTITUTION: In the semiconductor memory having plural sense amplifiers which are subjected to cascade connection, as a data read-out circuit part, a switch circuit is installed between the sense amplifiers which are subjected to cascade connection. That is, the switch circuit 101 is installed between the sense amplifier 111 of an initial stage for sensing a read-out data signal from a memory cell and the sense amplifier 121 of a final stage for driving an output buffer 141. In such a state, by a relation to sense amplifier control signals CA11, CA21, the switch circuit 101 is controlled by a control signal CL. In such a way, the read-out operation extending from the sense amplifier of the initial stage to the sense amplifier of the final stage can be executed by dividing it timewise, and the read-out operation can be executed by the data rate of a higher speed than that of a conventional semiconductor storage device.