PURPOSE: To shorten a writing time inverting the level of the storage information of a memory cell and to reduce power consumption at a writing time.

CONSTITUTION: Current source circuits are integrated to a first and a second current source circuits IS1, IS2 corresponding respectively to a first and a second digit lines DLj1, DLj2. The collector of a seventh transistor Qj3 is connected to the second digit line DLj2. The collector of the eighth transistor Qj4 is connected to the fiest digit line DLj1. Write control information DWj1, DWj2 decided from a column address signal ADc and write information DTw are inputted to the bases of the transistors Qj3, Qj4 respectively correspondingly. Thus, the transistor changing from on to off of the memory cell is separated from the current source circuit and current flowing through the transistor becomes zero rapidly, and power consumption is reduced since necessity making write current larger than read current is eliminated and write is ended in a short time.