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Title:
SEMICONDUCTOR MEMORY
Document Type and Number:
Japanese Patent JPS5610955
Kind Code:
A
Abstract:

PURPOSE: To contrive the extension of a memory retaining time of a semiconductor memory by forming a reverse conducting type diffused layer to a substrate between a memory cell and a carrier discharge source and applying prescribed constant voltage thereto to absorb minority carrier to the layer.

CONSTITUTION: A reverse polarity diffused layer 3 to a substrate is disposed between a memory cell 1 and a bootstrap circuit 2.The circuit 2 is an electron minority carrier discharge source in an N-channel and a hole minority carrier discharge source in a P-channel.The layer 3 is connected at the positions 5 to wiring layers 4, and a power supply voltage VDD is applied thereto. A constant voltage higher than the substrate is applied when the memory cell is N-channel, while the constant voltage lower than the substrate is applied when the memory cell is P-channel. Since the layer 3 absorbes the minority carrier to reduce the minority carrier reaching the memory cell 1 from the circuit 2 according to this configuration, it can extend the memory retaining time. It can also shorten the distance between the cell 1 and the source 2 so as to reduce the size thereof.


Inventors:
NAKAO MASUMI
Application Number:
JP8716579A
Publication Date:
February 03, 1981
Filing Date:
July 09, 1979
Export Citation:
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Assignee:
NIPPON ELECTRIC CO
International Classes:
H01L27/10; H01L21/822; H01L21/8242; H01L27/04; H01L27/105; H01L27/108; (IPC1-7): G11C11/40; H01L27/04; H01L27/06
Domestic Patent References:
JPS5068483A1975-06-07



 
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