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Title:
SEMICONDUCTOR MEMORY
Document Type and Number:
Japanese Patent JPS60182593
Kind Code:
A
Abstract:

PURPOSE: To rewrite the arbitrary bit width below the prescribed data width in a short time and to enhance using efficiency by driving selectively a bit selection multiplexer by means of a bit control signal and bit selection information.

CONSTITUTION: A control signal 100 causes write data 1010W101m-1 from data I/O buffers 70W7m-1 to be non-selection in data selection circuits 100W10m-1, selects bit data 102 from a bit data input buffer 11 and transmits them to cell write circuits 60W6m-1. A bit selection circuit 9 drives a bit selection line 104j corresponding to a bit position to be rewritten by a bit selection information 103, and gate selecting multiplexer gates 80,jW8n-1,j are made conductive. A column selection line 106i is selected by a row address information 105, and column selecting multiplexer gates 2i,0W2i,m-1 are made conductive, and bit lines 107i,0W 107i,m-1 are selected. On the other hand, a word line 109 is driven by a row address information 108, m×n units of cells are selected in one cell array and data are rewritten.


Inventors:
MASUMORI TADAAKI
UEOKA YASUSHIGE
NOMURA TOMOYOSHI
Application Number:
JP3733584A
Publication Date:
September 18, 1985
Filing Date:
March 01, 1984
Export Citation:
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Assignee:
NIPPON TELEGRAPH & TELEPHONE
International Classes:
G11C11/413; G11C11/34; G11C11/401; (IPC1-7): G11C11/34
Domestic Patent References:
JPS57147196A1982-09-10
JPS58194193A1983-11-12
JPS56130884A1981-10-14
Attorney, Agent or Firm:
Tsuneo Shiramizu



 
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