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Title:
SEMICONDUCTOR MEMORY
Document Type and Number:
Japanese Patent JPS6243897
Kind Code:
A
Abstract:

PURPOSE: To simplify mostly check by applying a mostly defect decision in a memory chip and outputting the result of decision externally.

CONSTITUTION: A n-bit counter 2 is carrried by an exclusive OR output 43 between input data 41 to a semiconductor memory and output data 42 of a semiconductor memory by an exclusive OR circuit 1. An output signal 45 of an output latch circuit 4 latching a AND signal 44 of count outputs 21W2n of the n-bit counter 2 by the AND circuit 3 is led to an output pad 5. A mostly permissible bit number is selected by the combination of the count outputs 21W21n, and when a semiconductor memory having a defective bit number within 2 bits is decided as a non-defective memory, the AND signal 44 is selected to be AND of the count output 21 and the count output 22.


Inventors:
TSUJIMOTO AKIRA
Application Number:
JP18332185A
Publication Date:
February 25, 1987
Filing Date:
August 20, 1985
Export Citation:
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Assignee:
NEC CORP
International Classes:
G11C29/00; G11C29/12; (IPC1-7): G11C29/00
Domestic Patent References:
JPS5448130A1979-04-16
JPS5673358A1981-06-18
JPS5564699A1980-05-15
Attorney, Agent or Firm:
Naoki Kyomoto (2 outside)



 
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