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Title:
SEMICONDUCTOR MEMORY
Document Type and Number:
Japanese Patent JPS6464193
Kind Code:
A
Abstract:

PURPOSE: To obtain a differential signal immune from the noise in the extrem by setting always a pair of capacities to the informational condition reverse in polarity, and deciding the memory condition of a cell with the differential output.

CONSTITUTION: A memory cell Cmn is formed in a depth direction between vertical bulkheads 51 and 51' on an n+ substrate 50 and has (p) layers 53 and 53' and a n+ substrate 54 under n+ layers 52 and 52'. The pp layers 55 is for controlling an FET characteristic. A cell Cmm is separated symmetrically to a pair of areas (a) and (b) by a bulkhead 56. The accumulated capacity is connected vertically by an insulation film 57 and an electrode 58, a switch FET is connected by a gate insulation film and a gate electrode 591 vertically to a substrate 50 and arranged symmetrically to the bulkhead 56. A gate electrode 591 is a part of a word line 592. The electrode 58 controls a conductance between a part extended to the (p) layer 53 an n+ layer 52 (bit line) through a gate insulation film 59 with the gate electrode 591 and executes the switch action. By the constitution, the cell is used in which a projected area is small and an accumulated capacity is larger per cell, and dRAM can be formed in which a noise resistance is large.


Inventors:
KETSUSAKO MITSUNORI
Application Number:
JP22014587A
Publication Date:
March 10, 1989
Filing Date:
September 04, 1987
Export Citation:
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Assignee:
HITACHI LTD
International Classes:
G11C11/405; G11C11/34; H01L21/8242; H01L27/10; H01L27/108; (IPC1-7): G11C11/34; H01L27/10
Attorney, Agent or Firm:
Katsuo Ogawa (1 person outside)