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Patent Searching and Data


Title:
SEMICONDUCTOR NON-VOLATILE MEMORY
Document Type and Number:
Japanese Patent JPS5958868
Kind Code:
A
Abstract:

PURPOSE: To stabilize the low voltage write/erase and read characteristic of a floating gate type semiconductor non-volatile memory cell by a method wherein the device is made to off-set structure and to the depletion type, and moreover a tunnel implantation region is provided at the part other than a channel region.

CONSTITUTION: Thick field oxide films 12 are provide at the circumferential parts of a P type semiconductor substrate 1 having P+ type interelement isolation regions 17 as the underlay, and a thin gate insulating film 5 is adhered on the channel region 4 consisting of the substrate 1 surrounded with the fixed oxide films thereof. Then a polycrystalline Si floating gate 6 is adhered extending from the upper part of the film 5 over the upper parts of the films 12, and an insulating film 7' is provided surrounding the floating gate thereof. After then, a polycrystalline Si control gate 8 is formed similarly on the film 7' corresponding to the film 5, a part of the film 7' on the film 12 on one side is removed, a newly thin insulating film 13 is adhered thereto, and a polycrystalline Si implanting gate 8' is adhered thereon. Then N type source.drain regions are formed by diffusion in the substrate 1 on both sides of the gate 6 according to the usual method.


Inventors:
KOMATSU MICHIO
Application Number:
JP16900582A
Publication Date:
April 04, 1984
Filing Date:
September 28, 1982
Export Citation:
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Assignee:
NIPPON ELECTRIC CO
International Classes:
H01L21/8247; H01L29/788; H01L29/792; (IPC1-7): G11C11/40
Attorney, Agent or Firm:
Uchihara Shin