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Title:
SEMICONDUCTOR NONVOLATILE RAM
Document Type and Number:
Japanese Patent JPS63209097
Kind Code:
A
Abstract:

PURPOSE: To obtain the semiconductor nonvolatile RAM of a low power consumption and of a low price by constituting it by connecting a nonvolatile MOS capacitor to a volatile RAM through a selection transistor.

CONSTITUTION: An N+ region 2, which is the output terminal Q of the volatile RAM, that two invertors are connected in series, and is the source region of a selection gate transistor (TR) T1, is formed on the surface of a P-type semiconductor substrate 1, and the selection gate TR T1, consisting of a selection gate insulation film 3 and a selection gate electrode 5, is connected in series, and further, the nonvolatile MOS capacitor C, consisting of a gate insulation film 4, a floating gate electrode 6, a control gate electrode 8 and an erasing terminal 10, is connected in series. Thus, because the power consumption at the time of a storing and a recall is small, and a structure is simple, the nonvolatile RAM of a low price and a low power consumption can be realized.


Inventors:
NAKANISHI AKISHIGE
Application Number:
JP4181987A
Publication Date:
August 30, 1988
Filing Date:
February 25, 1987
Export Citation:
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Assignee:
SEIKO INSTR & ELECTRONICS
International Classes:
G11C14/00; G11C11/40; G11C17/04; H01L21/8247; H01L27/10; H01L27/105; H01L29/78; H01L29/788; H01L29/792; (IPC1-7): G11C11/40; G11C17/04; H01L27/10; H01L29/78
Attorney, Agent or Firm:
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