Login| Sign Up| Help| Contact|

Patent Searching and Data


Title:
SEMICONDUCTOR OUTPUT CIRCUIT
Document Type and Number:
Japanese Patent JP2005130245
Kind Code:
A
Abstract:

To shorten the delay time in the change of an output voltage with respect to a turn-off signal, when a source follower constituted of an n-channel MOS transistor is turned off.

When the output voltage Vo is substantially equal to a power source voltage Vcc, the nMOS 37 discharges the electric charge of the gate of the source follower 32, on the basis of a control signal c for turning off the source follower from an on state. Then, when the output voltage Vo becomes lower than the power source voltage Vcc by the gate threshold voltage h of an nMOS 34a, 39E, the nMOS 34a goes to on state, the nMOS 37 goes to off state, and the nMOS 39E goes to on state, so as to allow the electric charge of the gate of the source follower 32 to be discharged more softly, as compared with nMOS 37. Consequently, when turning off the source follower 32, the delay time in the change of the output voltage Vo, with respect to the turn-off signal is shortened and also the generation of noise in the power source voltage Vcc is avoided.


Inventors:
NAKAHARA AKIHIRO
SOMA OSAMU
Application Number:
JP2003000364456
Publication Date:
May 19, 2005
Filing Date:
October 24, 2003
Export Citation:
Click for automatic bibliography generation   Help
Assignee:
NEC ELECTRONICS CORP
International Classes:
H02M1/08; H03K4/00; H03K17/04; H03K17/0412; H03K17/16; H03K17/687; H03K19/0175; (IPC1-7): H03K17/04; H02M1/08; H03K17/16; H03K17/687; H03K19/0175
Attorney, Agent or Firm:
西村 征生