PURPOSE: To reduce the channel length of a pull-up transistor and a pull-down transistor and to reduce a layout area by turning on the transistors weakly not setting potential supplied to the gate electrodes of the pull-up and pull-down transistors at VCC and VSS.

CONSTITUTION: A potential generation circuit 9 is comprised of a PMOS transistor 10 whose drain electrode is connected to a power source and whose gate electrode to a source, and a PMOS transistor 11 whose drain electrode is connected to the source of the PMOS transistor 10 and whose gate and source electrodes are grounded. The channel width to channel length ratio(W/L) of the transistor 11 is set at the one remarkably lower than that of the transistor 10. The potential which turns on a transistor 5 weekly is generated from the potential generation circuit 9. Thereby, it is possible to remarkably reduce the channel length of the transistor 5 compared with a conventional one, and to obtain a sufficient pull-up effect.