To provide an SRAM in which an erroneous writing to a nonselected column cell caused by the increase in the bit line load capacitance, resulting from the increase in the number of word lines, is prevented.

In a semiconductor storage circuit, plural memory cells are connected to a word line WA1. Data DAA1 on a bit line BA1 selected by a column signal COAL0 are written into the cell C11. During the writing, the potential of a substrate k of the inverter, which constitutes of a nonselected memory cell C12, is controlled to a prescribed potential, that differs from the potential of the selected cell C11. Thus, the malwriting to a nonselected memory cell is prevented.