PURPOSE: To decrease software errors and to attain miniaturization by inserting a transistor (TR) controlled by a mode signal in series with a 1-TR and 1 capacitor memory cell.

CONSTITUTION: When a word line 7 is brought to a high level and a mode line is brought to a low level, MOSFETs 1, 3 are both nonconductive and a capacitor 2 stores electric charge. When an α particle is made incident on a node N1 of a unit circuit 4 at the storage mode, the potential of the node N1 rises by the produced electric charge, the potential at a node N2 rises by the coupling of the capacitor 2 and its electric charge flows to the electrode of the FETs 1, 3. Since the potential of the semiconductor electrode is changed in a direction decreasing the potential difference between the electrode and the surrounding semiconductor, the electric charge is diffused quickly and the potential difference at the nodes N1, N2 is decreased. Thus the capacitor 2 holds most of the electric charge. Thus, the generation of software errors is prevented and the miniaturization of the circuit is attained.