Title:
半導体記憶装置
Document Type and Number:
Japanese Patent JP4170952
Kind Code:
B2
Abstract:
A memory cell array is configured to have a plurality of memory cells arranged in a matrix, each of the memory cells being connected to a word line and a bit line and being capable of storing n values (n is a natural number equal to or larger than 3). A control circuit controls the potentials of the word line and bit line according to input data and writes data into a memory cell. The control circuit writes data into the memory cell to a k-valued threshold voltage (k<=n) in a write operation, precharges the bit line once, and then changes the potential of the word line an i number of times to verify whether the memory cell has reached an i-valued (i<=k) threshold voltage.
Inventors:
Noboru Shibata
Tomoharu Tanaka
Tomoharu Tanaka
Application Number:
JP2004160165A
Publication Date:
October 22, 2008
Filing Date:
May 28, 2004
Export Citation:
Assignee:
Toshiba Corporation
International Classes:
G11C16/02; G11C11/34; G11C11/56; G11C16/04; G11C16/06; G11C16/12; G11C16/34
Domestic Patent References:
| JP2000076872A | ||||
| JP2001067884A | ||||
| JP10003792A | ||||
| JP2002324400A | ||||
| JP2002187020A | ||||
| JP10092186A | ||||
| JP2003196988A |
Attorney, Agent or Firm:
Takehiko Suzue
Satoshi Kono
Makoto Nakamura
Kurata Masatoshi
Sadao Muramatsu
Ryo Hashimoto
Satoshi Kono
Makoto Nakamura
Kurata Masatoshi
Sadao Muramatsu
Ryo Hashimoto