To provide a semiconductor memory device capable of simultaneously performing write of one piece of data and read of data by two read ports.

On a bit cell wherein a pair of driving transistors D1, D2, a pair of load transistors L1, L2, a pair of transmission transistors F1, F2, a pair of read-only transmission transistors FR1, FR2, and a pair of read-only driving transistors DR1, DR2 are included, a write word line WWL, a first read word line RWL1, a second read word line RWL2, a pair of write bit lines WBLt, WBLc, a first read bit line RBL1, and a second read bit line RBL2 are arranged.

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