PURPOSE: To obtain a ROM improved in high speed performance and noise resistance.

CONSTITUTION: Data is mask-programed in a memory cell array 101. An address buffer 14 is constituted of address latches 111a, 111b of two systems for fetching address data in time-division mode by clock synchronization and a selector 112 selecting the latch data concerned and outputting it. A data sense circuit 105 is constituted of sense amplifiers 113a, 113b of two systems for performing data sense and latch in time-division mode by clock synchronization and a selector 114 selecting the latch data concerned and outputting it. A clock generation circuit 107 generates a synchronizing clock signal for making these address buffer 104 and data sense circuit 105 perform time-division operation.