To provide a semiconductor storage that reduces the area of a row selection circuit and eliminates the influence of exposure, etching, or the like in manufacture for variations in the shape of a memory cell.

The semiconductor storage has: a word line selection circuit connected to a row address signal so that a desired word line is selected according to address input; and a pseudo word line potential fixation circuit connected to the word line of the pseudo memory cell. The pseudo word line potential fixation circuit is composed of NAND gates NANDR (i) (i=-1 to m+2) and inverters INVR(i) (i=-1 to m+2) as in the word line selection circuit, and the input of the pseudo word line potential fixation circuit is connected to the row address signal so that the word line of the pseudo memory cell always remains non-selected, thus making identical the configurations of circuits selecting and driving all word lines, reducing the area of the row selection circuit, and eliminating the influence of exposure, etching, or the like in manufacture.