Title:
SEMICONDUCTOR STORAGE
Document Type and Number:
Japanese Patent JP3169814
Kind Code:
B2
Abstract:
PROBLEM TO BE SOLVED: To reduce the power consumption while securing an area capable of accessing at random.
SOLUTION: This storage contains plural memory blocks 10-1 to 10-n, a memory block selection circuit 11 and a column decoder 12. Each of memory block 10-1 to 10-n is constituted of a memory cell part 104 constituted of plural word lines 101, plural bit line pairs 102, plural memory cells 103 and a peripheral circuit parts 105-107 which connect all memory cells of a row corresponding to row address of an input with the bit line pairs when a memory block selection signal to itself is active, and amplify the data read out on the bit line pairs 102 by a sense amplifier. An access control circuit 2 changes a block address and a column address while holding the row address in the fixed state, and makes random access to the memory cells in the same row of each of memory blocks 10-1 to 10-n.
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Inventors:
Yoshiharu Aimoto
Toru Kimura
Yoshikazu Yabe
Toru Kimura
Yoshikazu Yabe
Application Number:
JP31865495A
Publication Date:
May 28, 2001
Filing Date:
October 13, 1995
Export Citation:
Assignee:
NEC
International Classes:
G11C11/401; G11C7/00; G11C8/12; G11C11/407; (IPC1-7): G11C11/401; G11C7/00
Domestic Patent References:
| JP6414795A | ||||
| JP2244479A | ||||
| JP5182452A | ||||
| JP652680A | ||||
| JP5250867A |
Attorney, Agent or Firm:
Naoki Kyomoto