Title:
半導体構造およびその処理方法
Document Type and Number:
Japanese Patent JP3974930
Kind Code:
B2
Abstract:
A dual work function semiconductor structure with borderless contact and method of fabricating the same are presented. The structure may include a field effect transistor (FET) having a substantially cap-free gate and a conductive contact to a diffusion adjacent to the cap-free gate, wherein the conductive contact is borderless to the gate. Because the structure is a dual work function structure, the conductive contact is allowed to extend over the cap-free gate without being electrically connected thereto.
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Inventors:
Kiwi Ye
William Earl Tonty
Eugene Li
William Earl Tonty
Eugene Li
Application Number:
JP2006289044A
Publication Date:
September 12, 2007
Filing Date:
October 24, 2006
Export Citation:
Assignee:
INTERNATIONAL BUSINESS MASCHINES CORPORATION
Infineon Technologies North America Corp.
Infineon Technologies North America Corp.
International Classes:
H01L21/28; H01L21/336; H01L21/60; H01L21/768; H01L21/8234; H01L21/8238; H01L21/8242; H01L23/522; H01L27/088; H01L27/092; H01L27/108; H01L29/423; H01L29/43; H01L29/49; H01L29/78
Domestic Patent References:
| JP5251656A | ||||
| JP11330417A | ||||
| JP2002289701A |
Attorney, Agent or Firm:
Hiroshi Sakaguchi
Yoshihiro City
Yoshihiro City