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Patent Searching and Data


Title:
SEMICONDUCTOR SUBSTRATE APPEARANCE TEST EQUIPMENT
Document Type and Number:
Japanese Patent JPS6334943
Kind Code:
A
Abstract:

PURPOSE: To contrive reducing the required times for a movement and a test by previously enabling the preparation of pickup for the next test point during the test carried out by displaying in an image indicator after the test point of a semiconductor substrate is stored in a video signal delay memory circuit.

CONSTITUTION: A semiconductor substrate 10 mounted on an X-Y moving stage 8 is focused by a microscope 1 at the first previously set test point and a focused image is converted to an electrical video signal by a CCD camera 2 and amplified by a video signal amplifying circuit 3. The first test point is displayed in an image indicator 6 via a change-over circuit 4 which is in a full line state at the initial stage and a video signal distribution circuit 5 and simultaneously, the video signal for one screen of the image indicator is stored in a video signal delay memory circuit 7. Then, the stored video signal of the first test point is displayed in the image indicator 6 from the video signal delay memory circuit 7 by making the change-over circuit 4 a broken line state by operating a control desk 9 and the display is used for testing.


Inventors:
TAGAMI KAZUNORI
Application Number:
JP17969386A
Publication Date:
February 15, 1988
Filing Date:
July 29, 1986
Export Citation:
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Assignee:
KYUSHU NIPPON ELECTRIC
International Classes:
H01L21/66; G01N21/88; G01N21/956; (IPC1-7): G01N21/88; H01L21/66
Domestic Patent References:
JPS57111776A1982-07-12
Attorney, Agent or Firm:
Naoki Kyomoto (2 outside)