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Title:
SEMICONDUCTOR SUBSTRATE AND SEMICONDUCTOR DEVICE USING THE SAME
Document Type and Number:
Japanese Patent JP2005191247
Kind Code:
A
Abstract:

To provide a semiconductor substrate for manufacturing a vertical type device, in which a low ON-resistance of a vertical type MOSFET or the like is maintained, whereas a needed OFF breakdown strength can be ensured.

This semiconductor substrate is constituted, such that a high density arsenic layer 12 having a thickness of 0.5 to 3.0 μm is inserted in between a high density phosphorus layer 11 constituting the drain of the vertical-type MOSFET and an n-type drift layer 13. Thus, since the high-density arsenic layer 12 functions as a barrier layer which prevents phosphorus from spreading, from the high density phosphorus layer 11 to the n-type drift layer 13, the spread of a depletion layer, when turning off in the vertical-type MOSFET is ensured to enhance an OFF breakdown strength, and also the low ON resistance can be maintained.


Inventors:
OTANI KINYA
Application Number:
JP2003430267A
Publication Date:
July 14, 2005
Filing Date:
December 25, 2003
Export Citation:
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Assignee:
NEC ELECTRONICS CORP
International Classes:
H01L21/336; H01L29/08; H01L29/739; H01L29/78; H01L29/06; (IPC1-7): H01L29/78; H01L21/336
Domestic Patent References:
JPS63138767A1988-06-10
JPH0582791A1993-04-02
JPH08241993A1996-09-17
JPH04320377A1992-11-11
Attorney, Agent or Firm:
Kiyoshi Inagaki