To lower the occurrence of defective connections in wiring between semiconductor chips in a semiconductor system in which a plurality of semiconductor chips are mutually connected.
On a master chip 10, a slave chip 20 is mounted by connecting the chips 10 and 20 to each other through a first group of wirings 30-1 to 30-j and a second group of wiring 30-r for redundancy. The chips 10 and 20 are provided with connection rearranging wiring section 12, respectively, in addition to main circuits 11 and 21. Each wiring section 12 is provided with connection testing circuits 40A-1 to 40A-j and 40A-r which test the connections in the first group of wirings 30-1 to 30-j between the chips 10 and 20 and connection rearranging circuits 41A-1 to 41A-j and 41A-r which remedy failures by rearranging the connections in the wiring between the chips 10 and 20 by using the second group of wiring 30-r and making the first group of wirings 30-1 to 30-j unusable when defective connection is detected in the first group of wirings 30-1 to 30-j.
Next Patent: COMPOSITE MODULE AND ITS MANUFACTURING METHOD