Title:
SEMICONDUCTOR TEST APPARATUS FOR DETECTING FAIL OF BUILT-IN MEMORY
Document Type and Number:
Japanese Patent JP2005203085
Kind Code:
A
Abstract:
To provide a semiconductor test apparatus for detecting a fail of built-in memory.
A BIST circuit comprises: an address and control signal generator generating an address and a control signal responding to the control of a BIST controller; a test data generator generating test data; and a fail detector determining whether data outputted from the same address of the memory are the same mutually or not and detecting the propriety of the fail of a memory.
Inventors:
LEE HOI-JIN
Application Number:
JP2005004502A
Publication Date:
July 28, 2005
Filing Date:
January 11, 2005
Export Citation:
Assignee:
SAMSUNG ELECTRONICS CO LTD
International Classes:
G11C29/00; G11C29/02; G01R31/28; (IPC1-7): G11C29/00; G01R31/28
Attorney, Agent or Firm:
Makoto Hagiwara