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Patent Searching and Data


Title:
SEMICONDUCTOR TESTING APPARATUS
Document Type and Number:
Japanese Patent JP2004012389
Kind Code:
A
Abstract:

To provide a semiconductor testing apparatus for accurately carrying out checking operations of a board to be tested.

In the apparatus, a performance board 6 has a first mount surface 6x on which a socket 10 for mounting a device to be tested is arranged and a second mount surface 6y on which an external circuit 11 required for testing the device 9 is arranged. A recessed section 3a for containing the external circuit 11 is arranged at the center of a test head 3, and a plurality of connect pins 7 for connecting with the performance board 6 are arranged at the surroundings of the recessed section 3a, and pads for connecting with the connect pins 7 are formed on both the mount surfaces 6x, 6y of the performance board 6. Then, a testing measurement is carried out similarly whichever one of the first mount surface 6x and the second mount surface 6y of the performance board 6 is installed opposite to the test head 3.


Inventors:
KITAMURA HIROSHI
Application Number:
JP2002169048A
Publication Date:
January 15, 2004
Filing Date:
June 10, 2002
Export Citation:
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Assignee:
FUJITSU LTD
International Classes:
G01R31/28; G01R31/26; (IPC1-7): G01R31/26; G01R31/28
Attorney, Agent or Firm:
Hironobu Onda
Makoto Onda