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Patent Searching and Data


Title:
SEMICONDUCTOR TREATMENT SYSTEM, METHOD AND DEVICE
Document Type and Number:
Japanese Patent JP2000164475
Kind Code:
A
Abstract:

To optimize the manufacture of an integrated circuit by a method wherein individual substrate pieces are fixed on a support for applying to a heat treatment process at a temperature higher than a specified temperature, and after those substrate pieces are subjected to prescribed treatment, the substrate pieces are separated from each other.

A plurality of receiving spaces 9 are formed on a support or a skate holder 2, those spaces 9 are formed into oblique or slant holes and oblique or slant substrate pieces 1 are respectively arranged in the oblique or slant holes. After a prescribed treatment comprising a heat treatment process for forming an integrated circuit at a temperature of 450°C or higher is performed to the substrate pieces 1, a layer 3 deposited on the rear of the holder 2 is removed by etching or a treatment similar to the etching and the individual substrate pieces 1 are separated from the holes formed in the spacers 9. As a result, the easily optimized integraed circuit can be manufactured.


Inventors:
MEURIS MARK
MERTENS PAUL
HEYNS MARC
Application Number:
JP21517599A
Publication Date:
June 16, 2000
Filing Date:
July 29, 1999
Export Citation:
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Assignee:
IMEC INTER UNI MICRO ELECTR
International Classes:
H01L21/00; H01L21/02; H01L21/68; H01L29/06; (IPC1-7): H01L21/02
Domestic Patent References:
JPS6356942A1988-03-11
Attorney, Agent or Firm:
Aoyama Ryo (1 person outside)