PURPOSE: To execute an operation at a high speed and to read out the whole memory at a high speed by setting the operation of a sense amplifier to a data output state in the case of becoming the worst path before starting a read access.
CONSTITUTION: The sense amplifying circuit is provided with a pair of bit lines BL, the inverse of BL of each column of a memory cell array, a sense amplifying circuit SA for detecting and amplifying a potential difference of a pair of bit lines thereof, and an output potential setting part 10 for pre- charging (its) output node 1 to a prescribed potential in a pre-charge period. At the time of read-out operation of a memory, the operation of the sense amplifying circuit SA is set in advance so as to become a data output state in the case of becoming the worst path, therefore, no gate delay is generated. On the other hand, in the case of reading out data in the case of becoming the best path, the gate delay is shorter than the time of the worst path. In such a way, only the case of the best path comes to exist, its operation speed can be executed at a high speed, and the whole memory is read out at a high speed.
KASAI KAZUHIKO
MATSUO KENJI
KATO YOSHIHIRO
UMETSU KAZUAKI
TOSHIBA CORP
TOSHIBA ELETRONIC IWATE
| JPS60226092A | 1985-11-11 |