PURPOSE: To provide an automatic counting function by connecting the (n+1)th shift register SR to the output terminal of SRs of n-number of stages and detecting the output of the (n+1)th SR to generate a count output.
CONSTITUTION: An SRSn+1 is added to SRs S1∼Sn of n-number of stages, and the SRS2 is provided with a preset terminal PR, and SRs S3∼Sn are provided with reset terminals R. When reset signals R2 and R1 are given successively synchronously with a shift clock , SRs S3∼Sn+1 are set to "0", and the SRS2 is set to "1". After the reset operation, the SRS1 takes in serial data X and executes the data shifting operation synchronously with the clock . Data set to SRs S2∼Sn+1 are shifted simultaneously with this data shifting operation; and when n-number of data are inputted successively, "1" is set to the SRSn+1 for the first time after the reset processing due to the signal R2, and it is detected that n-number of shift clocks are counted, and a counting completion signal Y is outputted.
| JPH01269319 | REFERENCE SIGNAL GENERATION CIRCUIT |
| JPH0786879 | GENERATING CIRCUIT FOR PULSE OF 1:N DUTY RATIO |
KAMURO SETSUSHI
SAKAMOTO JITSUO
| JPS5851616A | 1983-03-26 | |||
| JPS5275140A | 1977-06-23 |