PURPOSE: To increase the degree of IC integration by transferring data in parallel from a shift register when the desired data is set to the shift register.

CONSTITUTION: The serial data SD and clock pulse CK are applied to a shift register 1, and the parallel output of the register 1 is added to a latch circuit 2 and a control circuit 3. A check code Ci is added to the transfer data series prior to the input of the transfer data to the circuit 2. The circuit 3 detects that the subsequent bit series equal to the transfer data when the input of the code Ci is through to the register 1. Then the circuit 3 opens the circuit 2 to latch the data when the input of the transfer data is through to the register 1.