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Title:
SERIAL DATA TRANSMITTING CIRCUIT
Document Type and Number:
Japanese Patent JPS58196724
Kind Code:
A
Abstract:

PURPOSE: To prevent a transmitting circuit from malfunctioning, by adding two flip-flops, an inverter, and a 3-input AND gate.

CONSTITUTION: An input signal Si is applied to a flip-flop 1, which is operated by a clock signal CL; and a flip-flop 2 is also operated similarly and their outputs Q1 and Q2 are applied to a latch circut 3 to be latched by a latch signal S1, transmitting them to output termnals C01 and C02. In this case, the output of a flip-flop 4 is inverted by an inverter 6 and applied to the 3-input AND gate 7 together with the outpt Q4 of the flip-flop 4 and the latch signal S1; and the latch signal 3 is put in operation by the output of the AND gate 7 to hold the last data even when the clock signal CL contains chattering or noise components, preventing the malfunction.


Inventors:
OOTANI MASAKI
Application Number:
JP8198982A
Publication Date:
November 16, 1983
Filing Date:
May 12, 1982
Export Citation:
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Assignee:
MITSUBISHI ELECTRIC CORP
International Classes:
H03M9/00; H04L25/40; (IPC1-7): H03K13/256; H04L25/02
Domestic Patent References:
JPS4835759A1973-05-26
Attorney, Agent or Firm:
Masuo Oiwa



 
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