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Title:
SERIAL INTERFACE CIRCUIT
Document Type and Number:
Japanese Patent JPH02107023
Kind Code:
A
Abstract:

PURPOSE: To prevent an unsettlement of parallel-to-sereial converter output in the transient time zone in which the supply voltage decreases by simultaneously inputting constant voltages to a parallel-serial converter in parallel when a specified time elapsed after the power source is disconnected.

CONSTITUTION: When a power source 50 to supply a standard voltage V to a parallel-serial converter 10 is disconnected, a detecting circuit 3 detects a time when the supply voltage drops from the standard voltage V for a constant time and goes to a certain value VLCUT or less, issues a detecting signal (d), and sends it to an output controller 2. At the normal time of the power source 50, the output controller 2 sends respective serial outputs Di1', to Din' to the parallel-serial converter 10, wherease, at the time of disconnecting the power source 50, they are controlled by the detecting signal (d) of the detecting circuit 3, and the controller 2 sends a constant voltage VC to the parallel-serial converter 10 in parallel. Thus, at the time of disconnecting the power source 50, since the constant voltage VC is inputted in parallel, and serially converted, the converted output of input data Di1 to Din cannot be obtained, but the disturbance of the serially converted output is not caused, and the adverse effect on a rear stage circuit is eliminated.


Inventors:
NOGUCHI TADANOBU
Application Number:
JP26015288A
Publication Date:
April 19, 1990
Filing Date:
October 14, 1988
Export Citation:
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Assignee:
FUJITSU LTD
International Classes:
H03M9/00; (IPC1-7): H03M9/00
Attorney, Agent or Firm:
Sadaichi Igita



 
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