PURPOSE: To execute the half duplex communication in an interface using serial/ parallel data for inputting and outputting by providing a tri-state buffer on a series-parallel signal input/output part.
CONSTITUTION: This circuit is provided with a shift register 3, a switching circuit 2 for switching a signal inputted and outputted to and from the shift register 3 to one of a series signal and a parallel signal, and a switching signal generating circuit 1 for generating a switching signal, and tri-state buffers 21-29 for bidirectional communication are contained in the switching circuit 2. By the switching signal generating circuit 1, the switching circuit 2 is divided into four states by a select signal of 2 bits. Also, four circuits are constituted by switching a signal inputted to the shift register 3 and a signal outputted from the shift register by the switching circuit 2. In such a way, the half duplex communication of a circuit in which series input/output is used as the interface, and a circuit in which parallel input/output is used as the interface can be attained.
IWATA SEIICHI
KUMAGAI SUSUMU
HITACHI COMMUNICATION SYSTEM