PURPOSE: To obtain an asymmetrical serial parallel conversion circuit by providing a means using asymmetrical input/output bit number, a circuit changing over a register circuit, a selector circuit, selectors, registers, and a counter circuit whose step number is varied.
CONSTITUTION: A means having nb of serial inputs, nb of serial output and 4nb of parallel input/output, a 4nb register circuit operating two functions of serial in/parallel out and parallel in /serial out by means of counter control corresponding to the input in succession to a register of a serial input stage and a selector circuit selecting the parallel out output of the register circuit and the parallel input at parallel/serial conversion are provided. Furthermor, a register circuit having a double buffer function bufferinga parallel conversion signal at serial/parallel conversion and a parallel input signal 1st stage latch function at parallel/serial conversion, a circuit identifying the two mode of serial/parallel conversion and parallel/ serial conversion and changing over the register and selector, and a counter circuit whose maximum step number is 4nb and whose step number is varied depending on the result of identification of a bit capacity being an object of conversion are provided.
KAMEDA HARUTOSHI
SAKIDA YASUHIKO
NAITO KUNIYOSHI
| JPS5844533A | 1983-03-15 | |||
| JPS5435644A | 1979-03-15 | |||
| JPS58170117A | 1983-10-06 | |||
| JPS57188153A | 1982-11-19 | |||
| JPS57186830A | 1982-11-17 |
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