To provide a serial-parallel converting circuit capable of inputting a status bit to a CPU in fixed circuit scale regardless of the number of bits of serial data.

The output of an AND gate 6 for a clock S3 and a mask signal 5 from a dual port RAM 5 is inputted to the clock of a shift register 4 to input serial data S1. The dual port RAM 5 writes the mask signal from a CPU 1 and receives the address signal of a counter 7 for inputting a frame S2 and clock S3.