PURPOSE: To improve the reliability, by detecting that the leading bit of an input serial signal is shifted to a prescribed shift stage of a shift register to output contents of the shift register in parallel.

CONSTITUTION: The serial signal having a length N is inputted to a terminal 11, and the output of the (N+1)-th shift stage of a shift register 2 is detected and is inputted to a gate 14 to which sampling pulses are inputted; and when the leading bit of the input serial signal is shifted to the (N+1)-th shift stage, a gate 12 is opened by the check passing output of a parity checking part 4 and the output of the gate 14, and a controlling counter 13 is operated to store the output of the shift register 2 in a memory 3. Consequently, the reliability is improved, and storing of defective data is avoided because the memory 3 and the shift state of the shift register 2 are related directly to each other.