PURPOSE: To increase an allowable phase shift quantity to facilitate discriminating pulses in a high-speed operation by extending the width of a discriminating clock to the width of a time slot of serial data and delaying the discriminating clock having the extended width by a time corresponding to the width of the time slot.

CONSTITUTION: A discriminating clock pulse (b) is counted to output a pulse (c), which has a width twice as long as the width of the discriminating clock pulse, from a counter 1. This pulse (c) is stored in a shift register by the discriminating clock pulse (b) and is shifted successively. A D flip flop 3 reads in the pulse by the rise of the first pulse (the first bit) of serial data and outputs "1" (h). The output of the D flip flop 3 is inputted to an NAND gate 7, and the NAND gate 7 sets a set terminal PR of the D flip flop 3 to "0", and therefore, output "1" of the D flip flop is fixed.