PURPOSE: To convert a digit serial data of digit expression added with code transmitted in digit serial or complement of 2 representation into a digit parallel data in high speed independently of the word length by providing a conversion table, gate delay and an output value selecting circuit to an output digit numeral generation circuit.

CONSTITUTION: An output digit numeral converting circuit 11 of a serial/parallel converting circuit outputs two digit numerals having a possibility to be an output code value to an input digit numeral from an input data line 10 to data lines 12 and 13. Further, a signal line 14 represents that the input digit numeral is not 0 and a code of the input digit numeral is outputted from a signal line 15. Two digit numerals from the lines 12, 13 are stored in registers 17W22 and each digit numeral of the registers 17W22 is selected and outputted by data selectors 23W25 for selecting the output digit numeral. The selectors 23W25 are controlled by output digit numeral selecting signals 34W36 outputted from output digit numeral selecting circuits 26W28 and a digit parallel data is outputted in high speed.