PURPOSE: To stably and properly parallelize serial data inputted at high speed, by combining two shift registers and two registers and reducing the influence of the delaying time and its fluctuation of elements constituting this circuit.

CONSTITUTION: A shift register SR1 successively outputs shift signals PB1∼PB4 of an input signal SD1 by delaying by τ/4∼τ/2 from the fall of a clock signal CLK2B and a register FF1 generates signals PO1∼PO4 from the signals PB1∼PB4 by delaying by τ/4∼τ/2 from the fall of the clock signal CLJ2B. Moreover, since another shift register SR2 successively reads and shifts the input signal SD1 at the fall of another clock signal CLK2C, output shift signals PE1∼PE4 are changed by delaying by τ/4∼τ/2 from the fall of the signal CLK2C. Since all the data of the signal SD1 are within a period of 3τ/2, within which the outputs PE1∼PE4 and PO1∼PO4 are included, the rising timing of a clock signal 4 is properly read by a register FF2 and the register FF2 outputs signals PD1∼PD8.