PURPOSE: To realize the serial parallel converting system not affected by the speed of a clock by providing plural serial parallel converting circuits and a latch circuit and performing latching in time division.
CONSTITUTION: A serial data A of n-bit constitution and a clock C synchronized with the data A are taken as inputs and m-set of serial parallel converting circuits (4-1∼4-m) and latch circuits (5-1∼5-m) are provided respectively. A signal of gates (6-1∼6-m) is received by a signal of a clock controller 8 frequency-dividing the clock C, forming the clock of n/m and performing the control, the signal is converted by n/m-bit each and each n/m-bit is latched by the signal of gates (7-1∼7-m). Thus, the time requiring to operate the latch circuits (5-1∼5-m) is the time for (n-n/m)-frequency-division, which is not affected by the clock speed.
MOROSAWA KENJI
KUCHITSU NOBORU
| JPS5179511A | 1976-07-10 |