PURPOSE: To execute easily a detection processing of a code of a specified pattern by outputting forcibly a parallel data being in a serial-parallel converting circuit at the time point, even at the timing by which a specified code detecting circuit has detected a specified code.

CONSTITUTION: A 12-bit shift register 61 converts successively an inputted serial data to a parallel data of 12 bits, and applies it to a comparing circuit 62. The parallel data of 12 bits and an EOL pattern of 12 bits applied from an EOL pattern circuit 63 are compared by the comparing circuit 63 at every clock, and when the coincidence is detected, an 8-bit register 3 is made write enable through an OR gate 7, and by the contents of an 8 bit shift register 2 of this time, the contents of an 8-bit register 3 are updated. Also, a 1/8 frequency dividing counter 4 is reset, and a transfer request signal is sent out to a DMA controller. When a transfer permitting signal is returned, a bus driver 5 is made enable, and the contents of the 8-bit register 3 are sent out to the bus by a parallel data format.