PURPOSE: To simplify the circuit counting the number of times of shift and to decrease the number of gates by providing one FF more than the number of shift stages 8 in addition to 8 flip-flops for shift when the number of bits (n)=8 and setting '1' to the head FF for shift with a preset signal at each 8 shift clocks.

CONSTITUTION: In giving 1 to terminals J and K of a JK flip-flop 59 and giving a clock to a terminal T, a shift clock having a half frequency of that of the clock is generated at a terminal Q. Since the level of the reset signal is '1', the output of an NAND circuit 63 goes to '1' and a preset signal is sent from an NOT circuit 65. The preset signal resets flip-flops 51∼57 and sets '1' to the flip-flop 50. When the flip-flop 57 is reset and the level of the terminal Q goes to '0', the flip-flop 58 goes to '0' at the next shift clock and the shift end signal restores to '0'. When the level 1 set to the flip-flop 50 is shifted again, the shift end signal is sent again.