PURPOSE: To attain the small scale of the circuit and the reduction in number of components by receiving a count signal as an address signal and outputting a stored data to a signal selection means, a serial signal converting means and a clock counter means respectively as a selection signal, the 1st clock and a clear signal.

CONSTITUTION: A selector counter 16 starts transmission by a transmission enable signal (g) and generates a counter signal (l). A control ROM 15 uses the counter signal (l) to generate a select signal (e), a parallel clock (k) and a counter stop signal (f). The selector 11 selects any of a data signal (a), a synchronizing signal (b) and an idle signal (c) by the select signal (e) and outputs the result as a parallel signal (d). A serial signal converting circuit 12 converts the parallel signal (d) into a serial signal (i) by using the parallel clock (k) and the serial data clock (h).